1. Field of the Invention
The invention relates to a control circuit including a circuit which generates a three-phase PWM (pulse width modulation) signal, and more particularly to a control circuit including a circuit for generating a three-phase PWM signal, and a circuit for carrying out feedback control for a three-phase invertor motor when the three-phase PWM signal is generated.
2. Description of the Related Art
FIG. 1 is a block diagram of a conventional circuit for generating a three-phase PWM signal.
The circuit for generating a three-phase PWM signal is comprised of a timer 21, a first compare register 22, a second compare register 24, a third compare register 26, a fourth compare register 28, a first buffer register 23, a second buffer register 25, a third buffer register 27, a fourth buffer register 29, an up- and down-counting flag 30, a first circuit 31 for generating a PWM signal, a second circuit 32 for generating dead time, and a third circuit 33 for controlling an output to be transmitted from the circuit.
The timer 21 generates a carrier period having a PWM waveform. If a carrier wave has a triangular waveform, the timer 21 carries out counting-up and counting-down operations.
The first compare register 22 controls a period of the timer 21. The first compare register 22 always makes comparison with an output transmitted from the timer 21, and converts an operation to be carried out by the timer 21 from counting-up operation to counting-down operation, if the first compare register 22 detects coincidence with the output signal transmitted from the timer 21.
The first compare register 22 generates first interruption 34, and the timer 21 generates second interruption 35.
The up- and down-counting flag 30 indicates a status of the timer 21. While the timer 21 is in counting-up operation, the up- and down-counting flag 30 is in a low level, whereas while the timer 21 is in counting-down operation, the up- and down-counting flag 30 is in a high level.
The second compare register 24 generates a U-phase timing. The second compare register 24 always makes comparison with an output signal transmitted from the timer 21, and outputs a coincidence signal or a one shot pulse signal, if the second compare register 24 detects coincidence with the output signal.
Similarly, the third compare register 26 generates a V-phase timing. The third compare register 26 always makes comparison with an output signal transmitted from the timer 21, and outputs a coincidence signal or a one shot pulse signal, if the third compare register 26 detects coincidence with the output signal.
Similarly, the fourth compare register 28 generates a W-phase timing. The fourth compare register 28 always makes comparison with an output signal transmitted from the timer 21, and outputs a coincidence signal or a one shot pulse signal, if the fourth compare register 28 detects coincidence with the output signal.
The coincidence signals generated by the second to fourth compare registers 24, 26 and 28 are transmitted to the first circuit 31. On receipt of the coincidence signals, the first circuit 31 generates a signal based on which positive-phase and opposite-phase signals in each of the phases are generated.
The signal generated in the first circuit 31 is transmitted to the second circuit 32. Based on the received signal, the second circuit 32 generates a timing to which dead time is added. Herein, dead time means a time for preventing positive and opposite phases of an invertor from short-circuiting with each other.
The second circuit 32 transmits its output signal to the third circuit 33, which then transmits U0, U1, V0, V1, W0 and W1 signals to terminals of a microcomputer.
FIG. 5 is a timing chart showing an operation of the timer 21, coincidence timings in the compare registers 22, 24, 26 and 28, and timings of the terminals.
A gap in a timing between U0 and U1 signals, a gap in a timing between V0 and V1 signals, and a gap in a timing between W0 and W1 signals are all equal to a dead time width.
As illustrated in FIG. 5, the first interruption 34 is generated by virtue of coincidence between the first compare register 22 and the timer 21. A timing at which the first interruption 34 is generated is a summit of a triangular wave carrier.
The second interruption 35 is generated by virtue of under-flow in the timer 21. A timing at which the under-flow is generated is a bottom of a triangular wave carrier.
In accordance with the timing chart of FIG. 5, the timer 21 makes triangular wave operation, and coincidence timings in the first to fourth compare registers 22, 24, 26 and 28 are symmetrical about a summit of the triangular wave. This is called a triangular wave carrier symmetrical mode.
A conventional circuit for generating a three-phase PWM signal operates in the above-mentioned manner.
A circuit for generating a three-phase PWM signal is generally designed to include a circuit for generating an analog-digital trigger, in order to conduct feedback control to a three-phase inverter motor.
Such a circuit for generating an analog-digital trigger has been conventionally used as an external circuit for a micro-computer. Because of recent demand of cost reduction, down-sizing of a substrate, and accurate control for effectively rotating a motor, it is presently required to conduct both control to a three-phase PWM signal and feedback control through a single micro-computer.
If feedback control is frequently conducted, a central processing unit (CPU) would have increased burden in dealing with data. Hence, there is also a demand of reduction in a time for dealing with data through software in CPU.
In particular, a system for simultaneously controlling a plurality of motors such as a fan motor or a compressor motor in an air-conditioner is accompanied with a serious problem of an increase in a time necessary for dealing with data through software in CPU.
In order to solve such a problem, for instance, Japanese Unexamined Patent Publication No. 9-121558 (A) has suggested a method of detecting a current in a PWM invertor by means of an analog-digital convertor.
In the suggested method, a current output from a PWM invertor is detected by an analog-digital convertor.
FIG. 3 is a block diagram illustrating a basic structure of a three-phase invertor motor. With reference to FIG. 3, a current output from a PWM invertor is detected at points Iu, Iv and Iw in the suggested method.
A timing at which a current output from a PWM invertor is detected is a lowest point in a PWM carrier. In other word, referring to FIG. 5 again, a timing at which a current output from a PWM invertor is detected is only a point corresponding to the second interruption 35.
However, it may be necessary to detect an output current of a PWM invertor at a point Ia in FIG. 3 in dependence on whether the three-phase invertor motor include a sensor and further on a structure of a system.
However, there cannot be found, in the suggested method, a concept of deviating an analog-digital conversion timing to a particular timing associated with a PWM output. Hence, the suggested method is inevitably accompanied with a problem that the suggested method can be applied only to a system in which currents Iu, Iv and Iw are directly detected.
Japanese Unexamined Patent Publication No. 4-172995 (A) has suggested a method of adjusting a timing at which a current output from an inverter is detected. The suggested method is carried out by means of an inverter additionally including only one compare register which generates a timing at which analog-digital conversion is to be carried out.
However, the suggested method is accompanied with problems that a time necessary for dealing with data through software is unavoidably long, because the compare register has one-stage structure, it would be quite difficult to generate two or more analog-digital timings, because the compare register has one-stage structure, it is impossible to select a plurality of analog-digital triggers, because an analog-digital trigger is connected merely to an analog-digital start, a burden for dealing with data through software is high, because a value is set in the compare register through software, and so on. Accordingly, the suggested method is not suitable to feedback control.
Japanese Unexamined Patent Publication No. 8-317685 (A) has suggested an invertor including a first unit for supplying AC power having a variable frequency, to an N-pole three-phase brushless DC motor, and matching a commercially available AC battery to thereby have DC battery, a second unit for converting power supplied from the first unit, to DC current, a third unit for detecting DC current output from the second unit, an invertor which converts DC current output from the second unit, into AC current having a variable frequency, and supplying the AC current to turns of the brushless DC motor, and a capacitor connected in parallel in three-phase between the invertor and the brushless DC motor.
Japanese Unexamined Patent Publication No. 8-261794 (A) has suggested an encoder including first means for generating an analog signal in dependence on a position of an object, second means for sampling the analog signal and converting the sampled analog signal to digital data, and third means for obtaining data indicative of a position of the object, based on the digital data, characterized by fourth means for estimating movement of the object during delay time necessary for sampling the analog signal and outputting data indicative of a position, based on newly sampled position data and previously sampled position data, and outputting both position data obtained by adding the estimated movement to the newly sampled position data, the estimated movement in a sampling period, and the newly sampled position data.
Japanese Unexamined Patent Publication No. 7-308071 (A) has suggested an invertor controller comprised of a plurality of switching devices, and converting DC voltage to AC voltage, characterized by first means for detecting a first voltage output from the invertor, second means for subtracting the first voltage from an instructed output voltage to thereby calculate a voltage error, third means for outputting compensation, based on an error voltage selected among respective phases of error voltages in accordance with whether which is greater among respective phases of the error voltages, fourth means for adding the selected compensation and the instructed output voltage to each other to calculate a duty voltage, and a PWM circuit receiving the duty voltage, and outputting a signal by which the switching devices are turned on or off, in accordance with the duty voltage.
Japanese Patent No. 2885256 (B2) has suggested a micro-computer which includes a signal generating circuit which generates a plurality of pulse width modulation (PWM) signals defined by a carrier wave, and which controls an object, based on the pulse width modulation signals. The signal generating circuit is comprised of a timer which outputs a signal which varies in the same way as a waveform defining the carrier wave, a control register which controls a period of the timer, a reload register which stores a count, and a plurality of control blocks transmitting the plurality of pulse width modulation signals, based on the signal output from the timer and the count stored in the reload register. Each of the control blocks is comprised of a compare register which always compares the signal output from the timer and a reference value to each other, and transmits a coincidence signal, if they are coincident with each other, a logic circuit which is set by an interruption signal output from the control register, and reset by the coincidence signal, a transfer register which transfers the reference value to the compare register at a predetermined timing, a one-shot timer into which the count stored in the reload register is set in synchronization with the logic circuit being set or reset, and means for generating the pulse width modulation signal, based on a signal output from the one-shot timer and a signal output from the logic circuit.
Japanese Unexamined Patent Publication No. 9-47065 (A) has suggested a motor controller including a dead time compensator which outputs AC voltage having a variable frequency from DC battery through a PWM-controlled invertor, to thereby drive a motor, control a motor current in feedback control, and compensate for voltage drop which occurs due to dead time. The motor controller further includes first means for sampling a motor current, second means for outputting an instruction indicative of a voltage, based on a current sampled by first means, third means for compensating for the instruction with the sampled current, fourth means for updating a voltage output from third means, as PWM instruction, and fifth means for successively operating first to fourth means at a predetermined period. First, third, fourth and second means are caused to operate in this order at timings generated by fifth means.
In view of the above-mentioned problems in the prior art, it is an object of the present invention to provide a control circuit which has functions of outputting a PWM signal and conducting feedback control both indispensable to three-phase invertor motor control, and which is able to be incorporated into a micro-computer.
It is also an object of the present invention to provide a control circuit which is capable of generating an analog-digital conversion timing by means of a circuit for generating an analog-digital trigger, without an increase in data to be dealt with through software.
In one aspect of the present invention, there is provided a control circuit including (a) a first circuit for generating a three-phase PWM (pulse width modulation) signal, the circuit having functions of generating a PWM signal necessary for driving a three-phase invertor motor, generating interruption at a carrier period, and generating interruption at an intermediate point of a carrier period, and (b) a second circuit for generating an analog-digital start trigger in synchronization with a timing at which the PWM signal is output.
It is preferable that the second circuit includes a first compare register having a two-staged structure, and a second compare register having a two-staged structure, and the first circuit includes a PWM timer. The first and second compare registers make comparison with an output signal transmitted from the PWM timer to thereby generate the analog-digital start trigger.
It is preferable that the first and second compare registers are automatically set up by automatic calculation of a timing at which the PWM signal is output.
It is preferable that the first circuit includes a PWM timer, and the second circuit generates two analog-digital start triggers, one of which is selected in synchronization with counting-up or counting-down operation of the PWM timer.
For instance, the control circuit may further include an auxiliary circuit including (a) a status flag which indicates whether analog-digital conversion is being carried out, (b) a detecting circuit which transmits a detection signal, when at least one of terminals which receive the PWM signal varies with respect to its status, and (c) an error flag setting circuit which sets an error flag when the detection signal is transmitted, while the status flag indicates analog-digital conversion is being carried out.
It is preferable that the error flag setting circuit generates interruption when the error flag has been set.
There is further provided a control circuit including (a) a first circuit for generating a three-phase PWM (pulse width modulation) signal, the circuit having functions of generating a PWM signal necessary for driving a three-phase invertor motor, generating interruption at a carrier period, and generating interruption at an intermediate point of a carrier period, and (b) a second circuit for generating an analog-digital start trigger in synchronization with a timing at which the PWM signal is output. The first circuit includes a PWM timer, and the second circuit includes (b1) first and second compare registers each of which makes comparison with an output signal transmitted from the PWM timer, and outputs a coincidence signal, (b2) first and second buffer registers associated with the first and second compare registers, respectively, and (b3) a third circuit which selects one of coincidence signals transmitted from the first and second compare registers, to thereby generate an analog-digital start trigger signal.
The control circuit may further include a register which stores a value reflecting a time necessary for carrying out analog-digital conversion in an analog-digital convertor equipped in a computer in which the control circuit is equipped in.
It is preferable that the second circuit further includes a selector which selects one of coincidence signals transmitted from the first and second compare registers, when the PWM timer is in counting-up operation, and selects the other, when the PWM timer is in counting-down operation.
It is preferable that the first circuit further includes a flag which indicates whether the PWM timer is in counting-up or counting-down operation, and transmits its output signal to the selector.
It is preferable that transfer to the first compare register from the first buffer register is carried out by interruption generated at under-flow in the PWM timer, if the PWM timer operates in a symmetrical triangle wave.
It is preferable that the first circuit further includes a flag which indicates whether the PWM timer is in counting-up or counting-down operation, and the third circuit is comprised of (b1) a first selector which receives coincidence signals transmitted from the first and second compare registers, (b2) a first latch device which receives a command transmitted from an external central processing unit, (b3) a second latch device which receives a command transmitted from an external central processing unit, and (b4) a second selector which receives both output signals transmitted from the first and second latch devices and an output signal transmitted from the flag, and transmits a selection signal to the first selector to indicate which one of the coincidence signals is to be selected.
The control circuit in accordance with the present invention is designed to include a circuit for generating an analog-digital trigger necessary for feedback control of a three-phase motor, as well as a circuit for outputting a three-phase PWM signal.
As is well known to those skilled in the art, a three-phase motor has three phase, that is, U-phase V-phase and W-phase. When these three phases are to be driven by means of an invertor, a micro-computer transmits a U control signal (PWM signal) and a U-bar control signal (PWM signal) for controlling U-phase, a V control signal (PWM signal) and a V-bar control signal (PWM signal) for controlling V-phase, and a W control signal (PWM signal) and a W-bar control signal (PWM signal) for controlling W-phase.
Herein, non-bared control signals are used for controlling an upper arm of an invertor, that is, a positive phase, and bared signals are used for controlling a lower arm of an invertor, that is, an opposite phase. Control signals to be input to upper and lower arms of an invertor are in inversion relation with each other, and further, are signals to which dead time is added for preventing active periods in an invertor from overlapping one another.
FIG. 2 is a block diagram of the control circuit in accordance with the present invention.
The control circuit is comprised of a first circuit 2 for generating a three-phase PWM signal, and a second circuit 1 for generating an analog-digital trigger. The first circuit 2 has three functions: the first function is to generate PWM signals necessary for a system for driving a three-phase motor by means of an invertor, that is, signals U0 and U1 for controlling upper and lower arms of a U-phase invertor, signals V0 and V1 for controlling a V-phase invertor, and signals W0 and W1 for controlling a W-phase invertor, and to output those signals to terminals; the second function is to generate the second interruption 35 at a carrier period; and the third function is to generate the first interruption 34 at an intermediate point of a carrier period.
The second circuit 1 is comprised of a first compare register 11 and a second compare register 13 both always making comparison with the timer 21 to thereby transmit a coincidence signal, a first buffer register 12 and a second buffer register 14 associated with the first compare register 11 and the second compare register 13, respectively, an A/D trigger selecting circuit 15 which selects one of the coincidence signals transmitted from the first and second compare registers 11 and 13, and outputs an analog-digital start trigger signal 16, and an A/D conversion time setting register 17 which stores a value reflecting a time necessary for conducting analog-digital conversion in an analog-digital convertor equipped in a micro-computer in which the control circuit in accordance with the present invention is also equipped.
Since the second circuit 1 outputs an analog-digital start trigger slightly before a timing at which U-phase varies, when the timer 21 is in counting-down operation, an output signal transmitted from the U-phase first buffer register 25 to which an output signal transmitted from the A/D conversion time setting register 17 is added is transmitted to the second buffer register 14.
Timings at which the first and second buffer registers 12 and 14 transfer their outputs to the first and second compare registers 11 and 13, respectively, are identical with timings at which the first to third buffer registers 25, 27 and 29 transfer their outputs to the first to third compare registers 24, 26 and 28, respectively, in the first circuit 2. That is, the timings are in synchronization with the second periodic interruptions 35 generated from the timer 21.
Designing compare registers to have such a two-staged structure as mentioned above makes it no longer necessary to consider a time necessary for dealing with data through software, because a value for a next period can be set in the previous period.
The A/D trigger selecting circuit 15 selects a coincidence signal transmitted from the first compare register 11 when the timer 21 is in counting-up operation, whereas selects a coincidence signal transmitted from the second compare register 13 when the timer 21 is in counting-down operation.
In order to switch a coincidence signal between the coincidence signals transmitted from the first and second compare registers 11 and 13, an up- and down-counting flag 30 holding status of the timer 21 as to whether the timer 21 is in counting-up or counting-down operation transmits its output signal to the A/D trigger selecting circuit 15.
Thus, the second circuit 1 automatically generates the analog-digital start trigger 16 in synchronization with a timing at which a three-phase PWM signal is output.
FIG. 3 is a circuit diagram of a circuit for controlling a three-phase motor by means of an invertor.
The terminals U0, U1, V0, V1, W0 and W1 of the first circuit 2, illustrated in FIG. 2, control U0, U1, V0, V1, W0 and W1 signals illustrated in FIG. 3.
In order to accurately control a three-phase motor, it would be necessary to always monitor rotation of the three-phase motor, and carry out control by which the monitored rotation is fed-back to a PWM control signal. Hereinbelow, such control is referred to as xe2x80x9cfeedback controlxe2x80x9d. In order to monitor rotation of a three-phase motor, it would be necessary to detect a U-phase current Iu, a V-phase current Iv and a W-phase current Iw in the three-phase motor by means of an analog-digital convertor.
There are known two methods of detecting those currents.
In the first method, the phase currents Iu, Iv and Iw are directly detected. In the first method, a timing at which analog-digital conversion is carried out is identical with PWM periodic interruption, and accordingly, the second interruption 35 illustrated in FIG. 2 can be used for A/D conversion. However, in order to accomplish analog-digital conversions simultaneously in three signals, each analog-digital conversion has to be carried out at a high rate.
In the second method, only a current running through a point Ia is detected. In the second method, since a sum of the currents Iu, Iv and Iw runs through the point Ia, it would be necessary to carry out analog-digital conversion at a timing at which each of the phase currents runs.
The second circuit 1 for generating an analog-digital trigger in the control circuit in accordance with the present invention makes it possible to carry out such analog-digital conversion. Though timing tuning has to be carried out in the second method, analog-digital conversion is carried out only once at one timing, and hence, the analog-digital conversion is not always necessary to be high-rate A/D conversion.
As having been explained so far, the control circuit in accordance with the present invention automatically generates an optimal analog-digital start trigger regardless of feedback control to be carried out in a three-phase motor. Accordingly, optimal feedback control can be accomplished in one micro-computer without an increase in dealing with data through software.
The advantages obtained by the aforementioned present invention will be described hereinbelow.
As having been explained so far, the control circuit in accordance with the present invention automatically generates an optimal analog-digital start trigger regardless of feedback control to be carried out in a three-phase motor. Accordingly, optimal feedback control can be accomplished in one micro-computer without an increase in dealing with data through software.
In addition, since each of the compare registers is designed to have a two-staged structure in the control circuit in accordance with the present invention, a value for a next period can be set in the previous period. As a result, it is no longer necessary to consider a time necessary for dealing with data through software, when data is dealt with.
The above and other objects and advantageous features of the present invention will be made apparent from the following description made with reference to the accompanying drawings, in which like reference characters designate the same or similar parts throughout the drawings.